1. Field of the Invention
The present invention relates to sensors, and more particularly, to image sensors and related methods.
2. Description of the Related Art
In general, CMOS image sensors include unit pixels, each having a photodiode and a MOS transistor. A CMOS image sensor sequentially detects a signal using a switching method to form an image.
FIG. 1 illustrates a ramp comparison analog-to-digital converter used in prior art CMOS image sensors. Referring to FIG. 1, ramp comparison analog-to-digital converter includes a plurality of pixels 11, a plurality of correlated double sampling (CDS) circuits 15, a ramp signal generator 21, a plurality of comparators 17, a counter 23, and a plurality of latches 19.
As each pixel 11 generates an electrical signal (for example, an analog signal) in response to incident light, the electrical signal is input to a CDS circuit 15 through a data line 13 coupled to the pixel. Each CDS circuit 15 receives an electrical signal, performs correlated double sampling, and outputs the sampled signal to a comparator 17 corresponding to the CDS circuit 15.
The ramp signal generator 21 outputs a ramp signal (OUT) in response to a ramp enable signal (EN1). Each of the plurality of comparators 17 receives the ramp signal through the (+) terminal, and the output signal of the CDS circuit 15 through the (−) terminal. The comparators 17 compare the received signals and provide comparison signals (COMP) (corresponding to results of the comparisons) to latches 19.
In response to a counter enable signal (EN2) the counter 23 begins counting, and the output signal of the counter 23 is provided to each latch 19.
FIG. 2 is a timing diagram of the operations of the converter of FIG. 1. Referring to FIGS. 1 and 2, the counter 23 and the ramp signal generator 21 are activated at the same time in response to respective enable signals (EN1, EN2). Accordingly, the counter 23 begins counting and each latch 19 latches each counted value.
If the level of the ramp signal (OUT) is higher than the level of the output signal of a CDS circuit 15, the output signal (COMP) of the respective comparator 17 transitions from a logic “low” level to a logic “high” level. In response to the state transition of the output signal (COMP) of the comparator 17, the latch 19 latches the received count value. Accordingly an analog signal generated by each pixel 11 is converted to a digital signal.
If there is no incident light to a pixel 11, the respective latch 19 will ideally output a digital signal “0”. However, even if there is no incident light on a pixel 11, the latch 19 may not output a digital signal “0” as a result of, for example, dark current resulting from leakage current in the pixel 11; an offset of CDS circuit 15; an offset of comparator 17; and/or an offset of ramp signal generator 21.
Accordingly, if offsets of the CDS circuit 15, the comparator 17, and/or the ramp signal generator 21 increase, the dynamic range of the ramp comparison analog-to-digital converter 10 may be reduced.